The present invention relates to LED lighting and, more Particularly, to a circuit for controlling the operations of LED lighting.
FIG. 1 is a schematic block diagram a conventional LED lighting system 100 comprising a set of 12 light-emitting diodes (LEDs) 102(1)-102(12) controlled by a matrix lighting controller (MLC) chip 110, where the LEDs 102 are connected to the MLC chip 110 via wires 104. The 12 LEDs 102 are connected in series between a constant-current source 106 and ground VSS. The voltage at the constant-current source 106 is 60V. In addition, each LED 102 is connected by a pair of wires 104 to a different transistor-based switch 112, where each switch 112 is in turn controlled by a different pulse-width modulation (PWM) driver 114.
FIG. 2 is a schematic circuit diagram showing a portion of the LED lighting system 100 of FIG. 1. In particular, FIG. 2 shows the constant-current source 106, the LEDs 102(10)-102(12), and their corresponding switches 112(10)-112(12) and wires 104, each of which contributes some amount of parasitic inductance. As shown in FIG. 2, the switch 112(11) comprises an n-type main transistor MN1, an n-type turn-off transistor MN2, and a turn-on switch S1, which is connected to a current source 113. Although not shown in FIG. 2, each of switches 112(10) and 112(12) has an analogous set of elements.
The switch 112(11) is opened by (i) opening the turn-on switch S1 and (ii) turning on the turn-off transistor MN2, which drains the gate of the main transistor MN1 to turn off the main transistor MN1. The switch 112(11) is closed by (i) turning off the turn-off transistor MN2 and (ii) closing the turn-on switch S1, which charges the gate of the main transistor MN1 to turn on the main transistor MN1. When the switch 112(11) is turned off, current from the constant-current source 106 passes through the LED 102(11), causing the LED 102(11) to emit light. When the switch 112(11) is turned on, the LED 102(11) is shorted, and the current instead passes through the switch 112(11), thereby bypassing the LED 102(11), which as a result will not emit light.
In general, the MLC chip 110 selectively turns on and off the switches 112(1)-112(12) to control the light emitted from the respective LEDs 102(1)-102(12). Note that, if switch 112(11) is off and switch 112(12) is on, then current will flow from left to right through the upper wire 104u. If switch 112(11) is off and switch 112(10) is on, then current will flow from right to left through the lower wire 104l. On the other hand, if switch 112(11) is on and switch 112(12) is off, then current will flow from right to left through the upper wire 104u. If switch 112(11) is on and switch 112(10) is off, then current will flow from left to right through the lower wire 104l. 
As shown in FIG. 1, the MLC chip 110 also has short-circuit (SC) detection circuitry 116 and open-circuit (OC) detection circuitry 118 designed to detect SC and OC conditions, respectively, in the individual LEDs 102 in order to detect faulty LEDs 102 and also to protect the corresponding switches 112. For example, if the LED 102(11) fails with an OC condition, then, when the corresponding switch 112(11) is turned off, the voltage across the LED 102(11)—and therefore the drain-to-source voltage Vds across the main transistor MN1—can get high enough to permanently damage the transistor MN1. To prevent that damage, the OC detection circuitry 118 is designed to quickly detect a high drain-to-source voltage Vds indicative of an OC condition and take appropriate measures, like quickly turning on the switch 112(11), in order to inhibit the drain-to-source voltage Vds from getting large enough to permanently damage the transistor MN1. During normal operations, the MLC chip 110 controls the relative timing of turning on and off the different switches 112(1)-112(12) to avoid over-voltage conditions from occurring.
Unfortunately, if the wires 104 that connect the MLC chip 110 to the LEDs 102 are sufficiently long, then the wires 104 will contribute enough parasitic inductance to result in false-positive detections of LED OC conditions by the OC detection circuitry 118. For example, if switch 112(11) is on and switches 112(10) and 112(12) are off, then current will flow down through the LED 102(12), from right to left through the upper wire 104u, down through switch 112(11), from left to right through the lower wire 104l, and down through the LED(10). If switch 112(11) is then turned off, the parasitic inductances in the upper and lower wires 104u and 104l will resist an instantaneous decrease in the current flowing through those wires, resulting in an induced drain-to-source voltage Vds across the transistor MN1. The longer the wires 104, the greater the parasitic inductance in the wires 104 and the greater the induced drain-to-source voltage Vds. In such cases, the OC detection circuitry 118 may misinterpret a high Vds as an OC condition in the corresponding LED(11). Note that, even if switch 112(10) and/or switch 112(12) is on, then other wires 104 will contribute parasitic inductances that can lead to false-positive detections of an OC condition in the LED(11).
FIG. 3 is a timing diagram showing certain signals associated with the operation of the LED lighting system 100 of FIGS. 1 and 2 when a false-positive detection of an OC condition occurs. At time t0, switch S1 is open and the turn-off transistor MN2 is on (i.e., the gate voltage G2 is high), which drives the gate voltage swg of the main transistor MN1 low and turns MN1 off. With MN1 off, the drain voltage swd of MN1 is high and the LED 102(11) is on. Thus, from time t0 to time t1, current is flowing through the LED 102(11) and no current is flowing through the switch 112(11).
At time t1, the gate voltage G2 is driven low to turn off the transistor MN2 and switch S1 is closed to drive the gate voltage swg high and turn on the transistor MN1, which drives the drain voltage swd of MN1 low and turns off the LED 102(11). Thus, from time t1 to time t2, no current is flowing through the LED 102(11) and instead current is flowing through switch 112(11) and, if switches 112(10) and 112(11) are both off, also through the corresponding wires 104u and 104l connecting the switch 112(11) to the LED 102(11).
At time t2, switch S1 is opened again and the gate voltage G2 of MN2 is again driven high to turn on MN2, which drives the gate voltage swg of MN1 low and turns off MN1. In this particular situation, the presence of parasitic inductances in the wires 104u and 104l cause the drain voltage swd of MN1 to rise and then oscillate in a damped manner. If the initial rise of the drain voltage swd is large enough, then the OC detection circuitry 118 will misinterpret the corresponding large drain-to-source voltage Vds as indicating an OC condition for LED 102(11).
It would be advantageous to provide circuitry that prevents such false-positive detection of OC conditions.